36 #include "uvm_macros.svh" 231 input bit <C_AXI_ADDR_WIDTH-1:0> address,
232 input bit <2:0> burst_size) {
239 aligned_address = address;
241 e_1BYTE : aligned_address = address;
242 e_2BYTES : aligned_address[0] = 0b0;
243 e_4BYTES : aligned_address[2] = 0b00;
244 e_8BYTES : aligned_address[3] = 0b000;
246 e_32BYTES : aligned_address[5] = 0b0_0000;
247 e_64BYTES : aligned_address[6] = 0b00_0000;
251 uvm_info(
"axi_pkg::calculatate-aligned_adress",
252 $sformatf(
"address: 0x%0x burst_size:%0d alignedaddress: 0x%0x",
253 address, burst_size, aligned_address),
256 return aligned_address;
273 input bit <C_AXI_ADDR_WIDTH-1:0> addr,
274 input
int bus_size) {
280 aligned_address = addr;
283 2**
e_1BYTE : aligned_address = addr;
284 2**
e_2BYTES : aligned_address[0] = 0b0;
285 2**
e_4BYTES : aligned_address[2] = 0b00;
286 2**
e_8BYTES : aligned_address[3] = 0b000;
287 2**
e_16BYTES : aligned_address[4] = 0b0000;
288 2**
e_32BYTES : aligned_address[5] = 0b0_0000;
289 2**
e_64BYTES : aligned_address[6] = 0b00_0000;
290 2**
e_128BYTES : aligned_address[7] = 0b000_0000;
295 $sformat(msg_s,
"%s addr: 0x%0x", msg_s, addr);
296 $sformat(msg_s,
"%s aligned_address: 0x%0x", msg_s, aligned_address);
297 $sformat(msg_s,
"%s bus_size: 0x%0x", msg_s, bus_size);
301 uvm_info(
"calculate_bus_aligned_address", msg_s,UVM_HIGH)
303 return aligned_address;
321 input bit <C_AXI_ADDR_WIDTH-1:0> addr,
322 input bit <2:0> burst_size,
323 input shortint burst_length) {
326 byte unalignment_offset;
327 shortint total_length;
336 .burst_size(burst_size));
338 total_length=burst_length + unalignment_offset;
340 shifter = shortint(total_length/(2**burst_size));
342 ishifter = shifter*(2**burst_size);
344 if (ishifter != total_length) {
352 $sformat(msg_s,
"%s addr: 0x%0x", msg_s, addr);
353 $sformat(msg_s,
"%s burst_size: %0d", msg_s, burst_size);
354 $sformat(msg_s,
"%s unalignment_offset: %0d", msg_s, unalignment_offset);
355 $sformat(msg_s,
"%s burst_length: %0d", msg_s, burst_length);
356 $sformat(msg_s,
"%s total_length: %0d", msg_s, total_length);
357 $sformat(msg_s,
"%s shifter: %0d", msg_s, shifter);
358 $sformat(msg_s,
"%s ishifter: %0d", msg_s, ishifter);
360 uvm_info(
"axi_pkg::calculate_beats",
375 input bit <C_AXI_ADDR_WIDTH-1:0> addr,
376 input byte burst_size) {
378 byte unalignment_offset;
381 e_1BYTE : unalignment_offset = 0;
382 e_2BYTES : unalignment_offset = byte(addr[0]);
383 e_4BYTES : unalignment_offset = byte(addr[2]);
384 e_8BYTES : unalignment_offset = byte(addr[3]);
385 e_16BYTES : unalignment_offset = byte(addr[4]);
386 e_32BYTES : unalignment_offset = byte(addr[5]);
387 e_64BYTES : unalignment_offset = byte(addr[6]);
388 e_128BYTES : unalignment_offset = byte(addr[7]);
391 return unalignment_offset;
407 input bit <C_AXI_ADDR_WIDTH-1:0> addr,
408 input bit <2:0> burst_size,
409 input shortint burst_length,
410 output bit <C_AXI_ADDR_WIDTH-1:0> Lower_Wrap_Boundary,
411 output bit <C_AXI_ADDR_WIDTH-1:0> Upper_Wrap_Boundary) {
419 .burst_size (burst_size),
420 .burst_length (burst_length)) + 1;
423 .burst_size(burst_size));
426 dtsize = (2**burst_size) * max_beat_cnt;
428 Lower_Wrap_Boundary = (int(Aligned_Address/dtsize) * dtsize);
429 Upper_Wrap_Boundary = Lower_Wrap_Boundary + dtsize;
448 input bit <C_AXI_ADDR_WIDTH-1:0> addr,
449 input bit <2:0> burst_size,
450 input shortint burst_length,
451 input bit <1:0> burst_type,
454 input
int data_bus_bytes) {
461 int Lower_Wrap_Boundary;
462 int Upper_Wrap_Boundary;
468 .burst_size (burst_size),
469 .burst_length (burst_length),
470 .Lower_Wrap_Boundary (Lower_Wrap_Boundary),
471 .Upper_Wrap_Boundary (Upper_Wrap_Boundary));
474 .burst_size (burst_size),
475 .burst_length (burst_length),
476 .burst_type (burst_type),
477 .beat_cnt (beat_cnt),
478 .data_bus_bytes(data_bus_bytes),
479 .Lower_Byte_Lane(Lower_Byte_Lane),
480 .Upper_Byte_Lane(Upper_Byte_Lane),
481 .offset(data_offset));
484 tmp_addr=addr+(lane - Lower_Byte_Lane);
485 }
else if (burst_type ==
e_INCR) {
486 tmp_addr=addr+data_offset+(lane - Lower_Byte_Lane);
488 }
else if (burst_type ==
e_WRAP) {
490 tmp_addr=addr+data_offset+(lane - Lower_Byte_Lane);
492 if (tmp_addr >= Upper_Wrap_Boundary) {
493 tmp_addr = Lower_Wrap_Boundary+(tmp_addr-Upper_Wrap_Boundary);
497 uvm_error(
"AXI_PKG::get_next_address", $sformatf(
"Unknown burst_type: %0d", burst_type))
502 $sformat(msg_s,
"%s beat_cnt:%0d", msg_s, beat_cnt);
504 $sformat(msg_s,
"%s lane:%0d", msg_s, lane);
505 $sformat(msg_s,
"%s Lower_Byte_Lane:%0d", msg_s, Lower_Byte_Lane);
506 $sformat(msg_s,
"%s Upper_Byte_Lane:%0d", msg_s, Upper_Byte_Lane);
507 $sformat(msg_s,
"%s Lower_Wrap_Boundary:%0d(0x%0x)", msg_s, Lower_Wrap_Boundary, Lower_Wrap_Boundary);
508 $sformat(msg_s,
"%s Upper_Wrap_Boundary:%0d(0x%0x)", msg_s, Upper_Wrap_Boundary, Upper_Wrap_Boundary);
509 $sformat(msg_s,
"%s number_bytes:%0d", msg_s, (2**burst_size));
510 $sformat(msg_s,
"%s data_offset:%0d", msg_s, data_offset);
511 $sformat(msg_s,
"%s tmp_addr:%0d(0x%0x)", msg_s, tmp_addr, tmp_addr);
513 uvm_info(
"axi_seq_item::get_next_address", msg_s, UVM_HIGH)
539 input bit <C_AXI_ADDR_WIDTH-1:0> addr,
540 input bit <2:0> burst_size,
541 input shortint burst_length,
542 input bit <1:0> burst_type,
544 input
int data_bus_bytes,
545 output
int Lower_Byte_Lane,
546 output
int Upper_Byte_Lane,
551 bit <63:0> Aligned_Start_Address;
552 bit <63:0> Address_N;
553 bit <63:0> Bus_Aligned_Address;
554 bit <63:0> Bus_Aligned_Address_N;
563 .burst_size(burst_size));
564 Address_N = Aligned_Start_Address+(beat_cnt*(2**burst_size));
571 .bus_size(data_bus_bytes));
573 .bus_size(data_bus_bytes));
579 Lower_Byte_Lane = addr - Bus_Aligned_Address;
580 Upper_Byte_Lane = Aligned_Start_Address + (2**burst_size) - 1 -
583 offset = beat_cnt*(2**burst_size);
589 Lower_Byte_Lane = addr - Bus_Aligned_Address;
590 Upper_Byte_Lane = Aligned_Start_Address + (2**burst_size) - 1 -
596 Lower_Byte_Lane = Address_N - Bus_Aligned_Address_N;
597 Upper_Byte_Lane = Lower_Byte_Lane + (2**burst_size) - 1;
599 offset = Address_N - addr;
604 $sformat(msg_s,
"%s beat_cnt:%0d", msg_s, beat_cnt);
605 $sformat(msg_s,
"%s data_bus_bytes:%0d", msg_s, data_bus_bytes);
606 $sformat(msg_s,
"%s NumberBytes (2**burst_size):%0d", msg_s, (2**burst_size));
608 $sformat(msg_s,
"%s addr:%0d", msg_s, addr);
609 $sformat(msg_s,
"%s Aligned_Start_Address:%0d", msg_s, Aligned_Start_Address);
610 $sformat(msg_s,
"%s Address_N:%0d", msg_s, Address_N);
611 $sformat(msg_s,
"%s Lower_Byte_Lane:%0d", msg_s, Lower_Byte_Lane);
612 $sformat(msg_s,
"%s Upper_Byte_Lane:%0d", msg_s, Upper_Byte_Lane);
613 $sformat(msg_s,
"%s offset:%0d", msg_s, offset);
615 uvm_info(
"axi_seq_item::get_beat_N_byte_lanes", msg_s, UVM_HIGH)
bit< AXI_SEQ_ITEM_W_NUM_BITS-1:0 > axi_seq_item_w_vector_t
Bit vector containing packed write data channel values.
byte calculate_unalignment_offset(input bit< C_AXI_ADDR_WIDTH-1:0 > addr, input byte burst_size)
calculate how unaligned the address is from the burst size
bit< C_AXI_LEN_WIDTH-1:0 > calculate_axlen(input bit< C_AXI_ADDR_WIDTH-1:0 > addr, input bit< 2:0 > burst_size, input shortint burst_length)
calculate awlen or arlen
parameter C_AXI_LEN_WIDTH
bit< AXI_SEQ_ITEM_AW_NUM_BITS-1:0 > axi_seq_item_aw_vector_t
Bit vector containing packed write address channel values.
localparam int AXI_SEQ_ITEM_R_NUM_BITS
logic< C_AXI_ID_WIDTH-1:0 > bid
logic< C_AXI_ID_WIDTH-1:0 > awid
logic< C_AXI_DATA_WIDTH/8-1:0 > wstrb
This packed struct is used to send read data channel information between the DUT and TB...
This packed struct is used to send write address channel information between the DUT and TB...
localparam int AXI_SEQ_ITEM_W_NUM_BITS
logic< C_AXI_DATA_WIDTH-1:0 > wdata
logic< C_AXI_DATA_WIDTH-1:0 > rdata
bit< C_AXI_ADDR_WIDTH-1:0 > get_next_address(input bit< C_AXI_ADDR_WIDTH-1:0 > addr, input bit< 2:0 > burst_size, input shortint burst_length, input bit< 1:0 > burst_type, input int beat_cnt, input int lane, input int data_bus_bytes)
Get next address for reading/writing to memory.
bit< C_AXI_ADDR_WIDTH-1:0 > calculate_burst_aligned_address(input bit< C_AXI_ADDR_WIDTH-1:0 > address, input bit< 2:0 > burst_size)
calculate burst_size aligned address
bit< AXI_SEQ_ITEM_R_NUM_BITS-1:0 > axi_seq_item_r_vector_t
Bit vector containing packed read data channel values.
logic< C_AXI_ID_WIDTH-1:0 > arid
burst_type_t
Does the address stay fixed, increment, or wrap during the burst?
response_type_t
Write response values.
parameter C_AXI_DATA_WIDTH
logic< C_AXI_ID_WIDTH-1:0 > wid
logic< C_AXI_ID_WIDTH-1:0 > rid
burst_size_t
Size of beat in bytes. (How many bytes of the data bus are used each beat(clk).
logic< C_AXI_ADDR_WIDTH-1:0 > araddr
bit< AXI_SEQ_ITEM_B_NUM_BITS-1:0 > axi_seq_item_b_vector_t
Bit vector containing packed write response channel values.
logic< C_AXI_ADDR_WIDTH-1:0 > awaddr
parameter C_AXI_ADDR_WIDTH
localparam int AXI_SEQ_ITEM_B_NUM_BITS
logic< C_AXI_LEN_WIDTH-1:0 > awlen
This packed struct is used to send write data channel information between the DUT and TB...
void get_beat_N_byte_lanes(input bit< C_AXI_ADDR_WIDTH-1:0 > addr, input bit< 2:0 > burst_size, input shortint burst_length, input bit< 1:0 > burst_type, input int beat_cnt, input int data_bus_bytes, output int Lower_Byte_Lane, output int Upper_Byte_Lane, output int offset)
return byte lanes that contain valid data
logic< C_AXI_LEN_WIDTH-1:0 > arlen
void calculate_wrap_boundary(input bit< C_AXI_ADDR_WIDTH-1:0 > addr, input bit< 2:0 > burst_size, input shortint burst_length, output bit< C_AXI_ADDR_WIDTH-1:0 > Lower_Wrap_Boundary, output bit< C_AXI_ADDR_WIDTH-1:0 > Upper_Wrap_Boundary)
calculate the wrap boundaries for a given burst
bit< C_AXI_ADDR_WIDTH-1:0 > calculate_bus_aligned_address(input bit< C_AXI_ADDR_WIDTH-1:0 > addr, input int bus_size)
calculate bus-siz aligned address
This packed struct is used to send write response channel information between the DUT and TB...
localparam int AXI_SEQ_ITEM_AW_NUM_BITS
localparam int AXI_SEQ_ITEM_AR_NUM_BITS
bit< AXI_SEQ_ITEM_AR_NUM_BITS-1:0 > axi_seq_item_ar_vector_t
Bit vector containing packed read address channel values.
This packed struct is used to send read address channel information between the DUT and TB...