Class List

Here are the classes, structs, unions and interfaces with brief descriptions:

[detail level 12]

Caxi_agent	Encapsulates driver, monitor, coverage collector, a local memory
Caxi_agent_config	Configuration object for an axi_agent
Caxi_base_test	Base test. AXI tests are to be extended from this test
Caxi_coveragecollector	Collects coverage
Caxi_driver	Logic to act as an AXI master for all 5 channels
Caxi_env	Creates two active AXI agents, one master and one slave/responder, plus a memory
Caxi_env_config	Configuration object for axi_env
Caxi_if_abstract	Abstract base class for polymorphic interface class (axi_if_concrete) for AXI UVM environment
Caxi_monitor	Monitors all 5 channels for activity
▼Caxi_pipelined_reads_seq	Backdoor memory writes, then reads from memory over AXI
Cmem_chk_s
Caxi_pipelined_reads_test	Pipelined AXI reads
▼Caxi_pipelined_writes_seq	Writes to memory over AXI, backdoor readback
Cmem_chk_s
Caxi_pipelined_writes_test	Pipelined AXI writes
Caxi_responder	Logic to act as an AXI slave (responder) for all 5 channels
Caxi_responder_seq	Forever running sequence that setups up responder *ready toggle patterns, then receives TLM packet from monitor and sends to responder
Caxi_scoreboard	Scoreboard
Caxi_seq	Writes to memory over AXI, backdoor readback, then AXI readback
Caxi_seq_item	All data and functions related to axi and usage
Caxi_seq_item_ar_vector_s	This packed struct is used to send read address channel information between the DUT and TB
Caxi_seq_item_aw_vector_s	This packed struct is used to send write address channel information between the DUT and TB
Caxi_seq_item_b_vector_s	This packed struct is used to send write response channel information between the DUT and TB
Caxi_seq_item_r_vector_s	This packed struct is used to send read data channel information between the DUT and TB
Caxi_seq_item_w_vector_s	This packed struct is used to send write data channel information between the DUT and TB
Caxi_sequencer	Normal sequencer with an extra analysis fifo and export
Caxi_sequential_reads_seq	Writes to memory over AXI, backdoor readback, then AXI readback
Caxi_sequential_reads_test	Sequential AXI reads. No pipelining
Caxi_sequential_writes_seq	Writes to memory over AXI, backdoor memory readback and verify
Caxi_sequential_writes_test	Sequential AXI writes. No pipelining
Cmemory	Extremely simple memory model with just write() and read() methods