AXI muckbucket
tb.sv
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1 //
3 // Copyright (C) 2017, Matt Dew @ Dew Technologies, LLC
4 //
5 // This program is free software (logic verification): you can redistribute it
6 // and/or modify it under the terms of the GNU Lesser General Public License (LGPL)
7 // as published by the Free Software Foundation, either version 3 of the License,
8 // or (at your option) any later version.
9 //
10 // This program is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
13 // for more details.
14 //
15 // License: LGPL, v3, as defined and found on www.gnu.org,
16 // http://www.gnu.org/licenses/lgpl.html
17 //
18 //
19 // Author's intent: If you use this AXI verification code and find or fix bugs
20 // or make improvements, then share those fixes or improvements.
21 // If you use this in a bigger project, I don't care about,
22 // or want, any changes or code outside this block.
23 // Example: If you use this in an SoC simulation/testbench
24 // I don't want, or care about, your SoC or other blocks.
25 // I just care about the enhancements to these AXI files.
26 // That's why I have choosen the LGPL instead of the GPL.
28 //
29 //module tb() {
38 
39 
40 
41  parameter C_AXI_ID_WIDTH = params_pkg::AXI_ID_WIDTH;
42  parameter C_AXI_ADDR_WIDTH = params_pkg::AXI_ADDR_WIDTH;
43  parameter C_AXI_DATA_WIDTH = params_pkg::AXI_DATA_WIDTH;
44  parameter C_AXI_LEN_WIDTH = params_pkg::AXI_LEN_WIDTH;
45 
46  #include "uvm_macros.svh"
47 
48 
49 
50 
51 
52  logic clk;
53  logic reset;
54 
55  wire axi_awready;
56  wire <C_AXI_ID_WIDTH-1:0> axi_awid;
57  wire <C_AXI_ADDR_WIDTH-1:0> axi_awaddr;
58  wire <C_AXI_LEN_WIDTH-1:0> axi_awlen; // Write Burst Length
59  wire <2:0> axi_awsize; // Write Burst size
60  wire <1:0> axi_awburst; // Write Burst type
61  wire <0:0> axi_awlock; // Write lock type
62  wire <3:0> axi_awcache; // Write Cache type
63  wire <2:0> axi_awprot; // Write Protection type
64  wire <3:0> axi_awqos; // Write Quality of Svc
65  wire axi_awvalid; // Write address valid
66 
67  // AXI write data channel signals
68  wire axi_wready; // Write data ready
69  wire <C_AXI_DATA_WIDTH-1:0> axi_wdata; // Write data
70  wire <C_AXI_DATA_WIDTH/8-1:0> axi_wstrb; // Write strobes
71  wire axi_wlast; // Last write transaction
72  wire axi_wvalid; // Write valid
73 
74  // AXI write response channel signals
75  wire <C_AXI_ID_WIDTH-1:0> axi_bid; // Response ID
76  wire <1:0> axi_bresp; // Write response
77  wire axi_bvalid; // Write reponse valid
78  wire axi_bready; // Response ready
79 
80  // AXI read address channel signals
81  wire axi_arready; // Read address ready
82  wire <C_AXI_ID_WIDTH-1:0> axi_arid; // Read ID
83  wire <C_AXI_ADDR_WIDTH-1:0> axi_araddr; // Read address
84  wire <C_AXI_LEN_WIDTH-1:0> axi_arlen; // Read Burst Length
85  wire <2:0> axi_arsize; // Read Burst size
86  wire <1:0> axi_arburst; // Read Burst type
87  wire <0:0> axi_arlock; // Read lock type
88  wire <3:0> axi_arcache; // Read Cache type
89  wire <2:0> axi_arprot; // Read Protection type
90  wire <3:0> axi_arqos; // Read Protection type
91  wire axi_arvalid; // Read address valid
92 
93 // AXI read data channel signals
94  wire <C_AXI_ID_WIDTH-1:0> axi_rid; // Response ID
95  wire <1:0> axi_rresp; // Read response
96  wire axi_rvalid; // Read reponse valid
97  wire <C_AXI_DATA_WIDTH-1:0> axi_rdata; // Read data
98  wire axi_rlast; // Read last
99  wire axi_rready; // Read Response ready
100 
101 // wire o_reset;
102  wire wb_cyc;
103  wire wb_stb;
104  wire wb_we;
105  wire <(C_AXI_ADDR_WIDTH-1):0> wb_addr;
106  wire <(C_AXI_DATA_WIDTH-1):0> wb_indata;
107  wire <(C_AXI_DATA_WIDTH-1):0> wb_outdata;
108  wire <(C_AXI_DATA_WIDTH/8-1):0> wb_sel;
109  wire wb_ack;
110  wire wb_stall;
111  wire wb_err;
112  int transactions;
113 
114 
116  axi_if <.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
117  .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
118  .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
119  .C_AXI_LEN_WIDTH (C_AXI_LEN_WIDTH)
120  > axi_driver_vif (.clk (clk),
121  .reset (reset),
122  .awready(axi_awready),
123  .awid(axi_awid),
124  .awaddr(axi_awaddr),
125  .awlen(axi_awlen),
126  .awsize(axi_awsize),
127  .awburst(axi_awburst),
128  .awlock(axi_awlock),
129  .awcache(axi_awcache),
130  .awprot(axi_awprot),
131  .awqos(axi_awqos),
132  .awvalid(axi_awvalid),
133 
134  .wready(axi_wready),
135  .wdata(axi_wdata),
136  .wstrb(axi_wstrb),
137  .wlast(axi_wlast),
138  .wvalid(axi_wvalid),
139 
140  .bid(axi_bid),
141  .bresp(axi_bresp),
142  .bvalid(axi_bvalid),
143  .bready(axi_bready),
144 
145  .arready(axi_arready),
146  .arid(axi_arid),
147  .araddr(axi_araddr),
148  .arlen(axi_arlen),
149  .arsize(axi_arsize),
150  .arburst(axi_arburst),
151  .arlock(axi_arlock),
152  .arcache(axi_arcache),
153  .arprot(axi_arprot),
154  .arqos(axi_arqos),
155  .arvalid(axi_arvalid),
156 
157  .rid(axi_rid),
158  .rresp(axi_rresp),
159  .rvalid(axi_rvalid),
160  .rdata(axi_rdata),
161  .rlast(axi_rlast),
162  .rready(axi_rready)
163  );
164 
166  axi_if <.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
167  .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
168  .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
169  .C_AXI_LEN_WIDTH (C_AXI_LEN_WIDTH)
170  > axi_responder_vif (.clk (clk),
171  .reset (reset),
172  .awready(axi_awready),
173  .awid(axi_awid),
174  .awaddr(axi_awaddr),
175  .awlen(axi_awlen),
176  .awsize(axi_awsize),
177  .awburst(axi_awburst),
178  .awlock(axi_awlock),
179  .awcache(axi_awcache),
180  .awprot(axi_awprot),
181  .awqos(axi_awqos),
182  .awvalid(axi_awvalid),
183 
184  .wready(axi_wready),
185  .wdata(axi_wdata),
186  .wstrb(axi_wstrb),
187  .wlast(axi_wlast),
188  .wvalid(axi_wvalid),
189 
190  .bid(axi_bid),
191  .bresp(axi_bresp),
192  .bvalid(axi_bvalid),
193  .bready(axi_bready),
194 
195  .arready(axi_arready),
196  .arid(axi_arid),
197  .araddr(axi_araddr),
198  .arlen(axi_arlen),
199  .arsize(axi_arsize),
200  .arburst(axi_arburst),
201  .arlock(axi_arlock),
202  .arcache(axi_arcache),
203  .arprot(axi_arprot),
204  .arqos(axi_arqos),
205  .arvalid(axi_arvalid),
206 
207  .rid(axi_rid),
208  .rresp(axi_rresp),
209  .rvalid(axi_rvalid),
210  .rdata(axi_rdata),
211  .rlast(axi_rlast),
212  .rready(axi_rready)
213  );
214 
215 
216  // tbx clkgen
217  {
218  clk = 0;
219  forever {
220  #10 clk = ~clk;
221  }
222 }
223 
224 // tbx clkgen
225  {
226  reset = 1;
227  #100 reset = 0;
228 }
229 
230  {
231 
232  if ($value$plusargs("transactions=%d", transactions)) {
233  uvm_info("plusargs", $sformatf("TRANSACTIONS: %0d", transactions), UVM_INFO)
234  }
235 
236  uvm_config_db <int> ::set(null, "*", "AXI_ADDR_WIDTH", C_AXI_ADDR_WIDTH);
237  uvm_config_db <int> ::set(null, "*", "AXI_DATA_WIDTH", C_AXI_DATA_WIDTH);
238  uvm_config_db <int> ::set(null, "*", "AXI_ID_WIDTH", C_AXI_ID_WIDTH);
239  uvm_config_db <int> ::set(null, "*", "AXI_LEN_WIDTH", C_AXI_LEN_WIDTH);
240 
241  axi_driver_vif.use_concrete_class();
242  axi_responder_vif.use_concrete_class();
243 
244  //run_test("axi_sequential_writes_test");
245  run_test();
246 
247 }
248 
249  {
250  $dumpfile("dump.vcd");
251  //$dumpvars(0, dut.axi_write_decoder); //(1);
252  $dumpvars(1); //(1);
253 
254 }
255 
256 }
C_AXI_LEN_WIDTH
parameter C_AXI_LEN_WIDTH
Definition: axi_pkg.sv:65
AXI_ID_WIDTH
parameter AXI_ID_WIDTH
Definition: params_pkg.sv:44
C_AXI_ID_WIDTH
parameter C_AXI_ID_WIDTH
Definition: axi_pkg.sv:41
AXI_LEN_WIDTH
parameter AXI_LEN_WIDTH
Definition: params_pkg.sv:47
C_AXI_DATA_WIDTH
parameter C_AXI_DATA_WIDTH
Definition: axi_pkg.sv:48
AXI_ADDR_WIDTH
parameter AXI_ADDR_WIDTH
Definition: params_pkg.sv:45
C_AXI_ADDR_WIDTH
parameter C_AXI_ADDR_WIDTH
Definition: axi_pkg.sv:59
axi_if
interface axi_if(input wire clk, input wire reset, inout wire awready, inout wire< C_AXI_ID_WIDTH-1:0 > awid, inout wire< C_AXI_ADDR_WIDTH-1:0 > awaddr, inout wire< C_AXI_LEN_WIDTH-1:0 > awlen, inout wire< 2:0 > awsize, inout wire< 1:0 > awburst, inout wire< 0:0 > awlock, inout wire< 3:0 > awcache, inout wire< 2:0 > awprot, inout wire< 3:0 > awqos, inout wire awvalid, inout wire wready, inout wire< C_AXI_DATA_WIDTH-1:0 > wdata, inout wire< C_AXI_DATA_WIDTH/8-1:0 > wstrb, inout wire wlast, inout wire wvalid, inout wire< C_AXI_ID_WIDTH-1:0 > bid, inout wire< 1:0 > bresp, inout wire bvalid, inout wire bready, inout wire arready, inout wire< C_AXI_ID_WIDTH-1:0 > arid, inout wire< C_AXI_ADDR_WIDTH-1:0 > araddr, inout wire< C_AXI_LEN_WIDTH-1:0 > arlen, inout wire< 2:0 > arsize, inout wire< 1:0 > arburst, inout wire< 0:0 > arlock, inout wire< 3:0 > arcache, inout wire< 2:0 > arprot, inout wire< 3:0 > arqos, inout wire arvalid, inout wire< C_AXI_ID_WIDTH-1:0 > rid, inout wire< 1:0 > rresp, inout wire rvalid, inout wire< C_AXI_DATA_WIDTH-1:0 > rdata, inout wire rlast, inout wire rready)
bindable interface for AXI UVM environment
Definition: axi_if.sv:39
AXI_DATA_WIDTH
parameter AXI_DATA_WIDTH
Definition: params_pkg.sv:46
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