Writes to memory over AXI, backdoor readback. More...

Inheritance diagram for axi_pipelined_writes_seq:

Collaboration diagram for axi_pipelined_writes_seq:

Classes
struct	mem_chk_s

Public Member Functions
	uvm_object_utils (axi_pipelined_writes_seq) axi_seq_item write_item[]

	new (string name="axi_pipelined_writes_seq")
	Constructor. More...

task	body ()
	Does all the work. More...

void	response_handler (uvm_sequence_item response)
	Handles write responses, including verifying memory via backdoor reads. More...

	uvm_object_utils (axi_seq) const int clearmemory=0

void	set_transaction_count (int count)
	How many transactions? More...

bit	compare_items (ref axi_seq_item write_item, ref axi_seq_item read_item)
	Compares the write-item with the corresponding read_item. More...

Public Attributes
int	transaction_id

event	writes_done

mem_chk_s	mem_chk_array [*]

const int	window_size = 0x1_0000

int	xfers_to_send = 1

bit	valid []

bit< 2:0 >	max_burst_size

int	xfers_done =0

memory	m_memory

Detailed Description

Writes to memory over AXI, backdoor readback.

Writes are pipelined so multiple in flight at once.

miscompares are flagged.

Definition at line 35 of file axi_pipelined_writes_seq.svh.

Class Documentation

struct axi_pipelined_writes_seq::mem_chk_s

Definition at line 48 of file axi_pipelined_writes_seq.svh.

Class Members
bit< ADDR_WIDTH-1:0 >	laddr
bit< ADDR_WIDTH-1:0 >	uaddr

Member Function Documentation

task axi_pipelined_writes_seq::body ( )

Does all the work.

Creates constrained random AXI write packet
Sends it
Backdoor read of memory to verify correctly written
Creates constrained random AXI read packet with same len and address as write packet
Sends it
Verifies read back data with written data.

two modes: Serial, Write_addr, then write, then resp. Repeat Parallel - Multiple write_adr, then multiple write_data, then multiple resp, repeat

Definition at line 131 of file axi_pipelined_writes_seq.svh.

References ADDR_WIDTH, e_WRITE, ID_WIDTH, axi_pipelined_writes_seq::mem_chk_s::laddr, axi_seq::m_memory, mem_chk_array, transaction_id, axi_pipelined_writes_seq::mem_chk_s::uaddr, axi_seq::valid, axi_seq::window_size, memory::write(), writes_done, axi_seq::xfers_done, and axi_seq::xfers_to_send.

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bit axi_seq::compare_items	(	ref axi_seq_item	write_item,
		ref axi_seq_item	read_item
	)

inherited

Compares the write-item with the corresponding read_item.

THis isn't the same as a do_compare() method in the axi_seq_item because the readback is depenent on which burst_type Although it could probably exist as aseperate method in the seqitem.

Parameters

write_item	- the original item
read_item	- the item after memory readback

Returns: True if no miscompares, false if miscompares

........................

Definition at line 115 of file axi_seq.svh.

References e_FIXED, e_INCR, e_WRAP, and axi_seq::max_burst_size.

axi_pipelined_writes_seq::new ( string name = "axi_pipelined_writes_seq" )

Constructor.

Doesn't actually do anything except call parent constructor

Definition at line 113 of file axi_pipelined_writes_seq.svh.

automatic void axi_pipelined_writes_seq::response_handler ( uvm_sequence_item response )

Handles write responses, including verifying memory via backdoor reads.

Definition at line 67 of file axi_pipelined_writes_seq.svh.

References ADDR_WIDTH, axi_seq_item::cmd, axi_seq_item::convert2string(), e_WRITE_RESPONSE, axi_seq_item::id, axi_pipelined_writes_seq::mem_chk_s::laddr, axi_seq::m_memory, mem_chk_array, memory::seq_item_check(), axi_pipelined_writes_seq::mem_chk_s::uaddr, axi_seq::xfers_done, and axi_seq::xfers_to_send.

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void axi_seq::set_transaction_count ( int count )

inherited

How many transactions?

This method sets how many transactions to send (Write Address, Write Data, Write Response) is one traction (Read Address, Read Data) is one transaction

Parameters

count - how many transactions to send

Definition at line 92 of file axi_seq.svh.

References axi_seq::xfers_to_send.

Referenced by axi_base_test::build_phase().

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