axi_driver.svh

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//
// Copyright (C) 2017, Matt Dew @ Dew Technologies, LLC
//
// This program is free software (logic verification): you can redistribute it
// and/or modify it under the terms of the GNU Lesser General Public License (LGPL)
// as published by the Free Software Foundation, either version 3 of the License,
// or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public License
// for more details.
//
// License: LGPL, v3, as defined and found on www.gnu.org,
//      http://www.gnu.org/licenses/lgpl.html
//
//
// Author's intent:  If you use this AXI verification code and find or fix bugs
//                   or make improvements, then share those fixes or improvements.
//                   If you use this in a bigger project, I don't care about,
//                   or want, any changes or code outside this block.
//                   Example: If you use this in an SoC simulation/testbench
//                            I don't want, or care about, your SoC or other blocks.
//                            I just care about the enhancements to these AXI files.
//                   That's why I have choosen the LGPL instead of the GPL.

class axi_driver : public uvm_driver <axi_seq_item>  { public: 
  uvm_component_utils(axi_driver)

  axi_if_abstract     vif;
  axi_agent_config    m_config;
  memory              m_memory;

  mailbox <axi_seq_item>  writeaddress_mbx  = new(0);  //unbounded mailboxes
  mailbox <axi_seq_item>  writedata_mbx     = new(0);
  mailbox <axi_seq_item>  writeresponse_mbx = new(0);
  mailbox <axi_seq_item>  readaddress_mbx   = new(0);
  mailbox <axi_seq_item>  readdata_mbx      = new(0);

   new (string name="axi_driver", uvm_component parent=null);

   void build_phase     (uvm_phase phase);
   void connect_phase   (uvm_phase phase);
  task          run_phase       (uvm_phase phase);

  task          write_address   ();
  task          write_data      ();
  task          write_response  ();
  task          read_address    ();
  task          read_data       ();


};

 axi_driver::new (string name = "axi_driver", uvm_component parent = null) {
  super.new(name, parent);
}

 void axi_driver::build_phase (uvm_phase phase) {
  super.build_phase(phase);

  vif = axi_if_abstract::type_id::create("vif", this);
}

 void axi_driver::connect_phase (uvm_phase phase) {
  super.connect_phase(phase);
}


task axi_driver::run_phase(uvm_phase phase) {

  axi_seq_item item;

    fork
       write_address();
       write_data();
       write_response();
       read_address();
       read_data();
    join_none


  forever {

    seq_item_port.get(item);

    uvm_info(this.get_type_name(),
              $sformatf("Item: %s", item.convert2string()),
              UVM_INFO)

    case  (item.cmd) { 
      axi_uvm_pkg::e_WRITE : {
        writeaddress_mbx.put(item);
      }
      axi_uvm_pkg::e_READ  : {
        readaddress_mbx.put(item);
      }

   }

  } // forever

}


task axi_driver::write_address() {

  axi_seq_item item=null;
  axi_seq_item_aw_vector_s v;

  bit <ADDR_WIDTH-1:0>  aligned_addr;

  bit <7:0>  wdata [];
  bit wstrb [];

  int minval;
  int maxval;
  int wait_clks_before_next_aw;


  vif.set_awvalid(0b0);

  vif.wait_for_not_in_reset();

  forever {

    if (item == null) {
       writeaddress_mbx.get(item);
      uvm_info("axi_driver::write_address",
                $sformatf("Item: %s", item.convert2string()),
                UVM_HIGH)

       axi_uvm_pkg::aw_from_class(.t(item), .v(v));
    }

    vif.wait_for_clks(.cnt(1));

      // if done with this xfer (write address is only one clock, done with valid & ready
       if (vif.get_awready_awvalid == 0b1) {
          writedata_mbx.put(item);
          item=null;

          minval=m_config.min_clks_between_aw_transfers;
          maxval=m_config.max_clks_between_aw_transfers;
          wait_clks_before_next_aw=$urandom_range(maxval,minval);

          // Check if delay wanted
          if (wait_clks_before_next_aw==0) {
             // if not, check if there's another item

            if (writeaddress_mbx.try_get(item)) {
                    uvm_info("axi_driver::write_address",
                $sformatf("Item: %s", item.convert2string()),
                UVM_HIGH)

                axi_uvm_pkg::aw_from_class(.t(item), .v(v));
             }
          }
       }
       // Initialize values  <-no need

       // Update values <- No need in write address (only one clk per)

       // Write out
       if (item != null) {
          vif.write_aw(.s(v), .valid(0b1));
       }  else {// if (item != null)

    // No item for next clock, so close out bus
         v.awaddr  = 0x0;
         v.awid    = 0x0;
         v.awsize  = 0x0;
         v.awburst = 0x0;
         vif.write_aw(.s(v), .valid(0b0));


        if (wait_clks_before_next_aw > 0) {
           vif.wait_for_clks(.cnt(wait_clks_before_next_aw-1)); // -1 because another wait
                                                                // // at beginning of loop
        }
    }


    } // forever

}

task axi_driver::write_data() {
  axi_seq_item item=null;
  axi_seq_item_w_vector_s s;

  bit <7:0>  wdata[];
  bit      wstrb[];

  int n=0;

  int minval;
  int maxval;
  int wait_clks_before_next_w;
  int beat_cntr=0;
  int beat_cntr_max;
  int validcntr;
  int validcntr_max;
  int j;
  int valid_asserts;
  int valid_assert_bit;

  int clks_without_wvalid_or_wready;

  vif.set_wvalid(0b0);
  forever {

    if (item == null) {
       writedata_mbx.get(item);

       if (m_config.wvalid.size > 0) {
         item.valid=new[m_config.wvalid.size](m_config.wvalid);
       } else {
         item.valid=new[item.len];
         for (int i=0;i <item.len;i++) {
           item.valid[i]=$random;
         }
       }

       valid_asserts = 0;
       j=item.valid.size();
       for (int i=0;i <j;i++) {
          item.valid[i] = $random;
         if (item.valid[i] == 0b1) {
             valid_asserts++;
          }
       }


       // valid must be asserted at least once to avoid never sending data.
       if (valid_asserts==0) {
          valid_assert_bit=$urandom_range(j-1,0);
          item.valid[valid_assert_bit] = 0b1;
          uvm_info("axi_driver::write_data",
                    $sformatf("All zeros. Settin bit %0d to 1", valid_assert_bit),
                    UVM_HIGH)
       }


      validcntr=0;
      validcntr_max=item.valid.size();

      beat_cntr=0;
      beat_cntr_max=axi_pkg::calculate_axlen(.addr(item.addr),
                                             .burst_size(item.burst_size),
                                             .burst_length(item.len)) + 1;

      clks_without_wvalid_or_wready=0;
      uvm_info("axi_driver::write_data",
                $sformatf("Item: %s", item.convert2string()),
                UVM_HIGH)

    }


    vif.wait_for_clks(.cnt(1));


    // Check if done with this transfer

    if (vif.get_wready()==0b1 && vif.get_wvalid() == 10b1) {

      beat_cntr++;

      uvm_info("axi_driver::write_data",
                $sformatf("beat_cntr:%0d  beat_cntr_max: %0d", beat_cntr, beat_cntr_max),
                UVM_HIGH)


      if (beat_cntr >= beat_cntr_max) {
          writeresponse_mbx.put(item);
          item = null;


          minval=m_config.min_clks_between_w_transfers;
          maxval=m_config.max_clks_between_w_transfers;
          wait_clks_before_next_w=$urandom_range(maxval,minval);

          // Check if delay wanted
          if (wait_clks_before_next_w==0) {
             // if not, check if there's another item

            if (writedata_mbx.try_get(item)) {
                  uvm_info("axi_driver::write_data",
                $sformatf("Item: %s", item.convert2string()),
                UVM_HIGH)

                if (m_config.wvalid.size > 0) {
                   item.valid=new[m_config.wvalid.size](m_config.wvalid);
                } else {
                   item.valid=new[item.len];
                  for (int i=0;i <item.len;i++) {
                      item.valid[i]=$random;
                   }
                }

                valid_asserts = 0;
                j=item.valid.size();
                for (int i=0;i <j;i++) {
                   item.valid[i] = $random;
                  if (item.valid[i] == 0b1) {
                       valid_asserts++;
                   }
                }


                // valid must be asserted at least once to avoid never sending data.
              if (valid_asserts==0) {
                   valid_assert_bit=$urandom_range(j-1,0);
                   item.valid[valid_assert_bit] = 0b1;
                   uvm_info("axi_driver::write_data",
                             $sformatf("All zeros. Settin bit %0d to 1", valid_assert_bit),
                             UVM_HIGH)
                }

                validcntr=0;
                validcntr_max=item.valid.size();

                beat_cntr=0;
                beat_cntr_max=axi_pkg::calculate_axlen(.addr(item.addr),
                                                       .burst_size(item.burst_size),
                                                       .burst_length(item.len)) + 1;
                clks_without_wvalid_or_wready=0;
            }

          }
       }
    }  // (vif.get_wready()==1'b1 && vif.get_wvalid() == 1'b1)


    // Update values
    if (item != null) {
       // if too long withoutsending any data, then add an extra valid.
       // it is entirely possible for ready and valid to not have overlap,
       // which will hang the sim.  Add additional valids to counteract.
       // \Todo: Need to report all this to help with reproducing bugs
       if (vif.get_wready()==0b0 && vif.get_wvalid() == 10b0) {
          clks_without_wvalid_or_wready++;
          if (clks_without_wvalid_or_wready > m_config.clks_without_wvalid_or_wready_max) {
            j=item.valid.size();

            valid_assert_bit=$urandom_range(j-1,0);
            item.valid[valid_assert_bit] = 0b1;
            uvm_info("axi_driver::write_data",
                      $sformatf("%0d clocks without ready/valid overlap.  Setting another valid[], bit %0d, to 1", clks_without_wvalid_or_wready, valid_assert_bit),
                      UVM_INFO)
            clks_without_wvalid_or_wready=0;
         }
       }

       s.wvalid = item.valid[validcntr]; // 1'b1;

      uvm_info(this.get_type_name(),
                $sformatf("Calling get_beat_N_data:  %s",
                          item.convert2string()),
                UVM_HIGH)

      item.get_beat_N_data(.beat_cnt(beat_cntr),
                           .data_bus_bytes(vif.get_data_bus_width()/8),
                            .data(wdata),
                            .wstrb(wstrb),
                            .wlast(s.wlast));

      for (int x=0;x <vif.get_data_bus_width()/8;x++) {
        s.wdata[x*8+:8] = wdata[x];
        s.wstrb[x]      = wstrb[x];
      }

       // Write out
       vif.write_w(.s(s));


       // if invalid-toggling-mode is enabled, then allow deasserting valid
       // before ready asserts.
       // Default is to stay asserted, and only allow deasssertion after ready asserts.
       if (vif.get_wready()==0b1 && vif.get_wvalid() == 10b1) {
          validcntr++;
          uvm_info(this.get_type_name(),
                    $sformatf("debuga validcntr=%0d",validcntr),
                    UVM_HIGH)
       } else if (m_config.axi_incompatible_wvalid_toggling_mode == 0b1) {
         validcntr++;
         uvm_info(this.get_type_name(),
                   $sformatf("debugb validcntr=%0d",validcntr),
                UVM_HIGH)
       } else if (vif.get_wvalid() == 0b0) {
         validcntr++;
         uvm_info(this.get_type_name(),
                   $sformatf("debugc validcntr=%0d",validcntr),
                UVM_HIGH)

        }
       if (validcntr >=  validcntr_max) {
         validcntr=0;
       }


    } // (item != null)

    // No item for next clock, so close out bus
    if (item == null) {
       s.wvalid = 0b0;
       s.wlast  = 0b0;
       s.wdata  = 0x0;
 //    s.wid    = 'h0; AXI3 only
       s.wstrb  = 0x0;

       vif.write_w(.s(s));

       if (wait_clks_before_next_w > 0) {
          vif.wait_for_clks(.cnt(wait_clks_before_next_w-1));
                                        // -1 because another wait
                                        // at beginning of loop
       }
    } // if (item == null
  } // forever
}




task axi_driver::write_response() {

  axi_seq_item            item;
  axi_seq_item_b_vector_s s;

  vif.enable_bready_toggle_pattern(m_config.bready_toggle_pattern);

  // \todo: Ch to be like others. wait for write_resonse, add to quque, then
  // process.
  // // need timeout on get ???

  forever {
    writeresponse_mbx.get(item);

    item.cmd = e_WRITE_RESPONSE;
    vif.wait_for_write_response(.s(s));
    item.bid   = s.bid;
    item.bresp = s.bresp;
    seq_item_port.put(item);


  }
}


task axi_driver::read_address() {

  axi_seq_item item=null;
  axi_seq_item_ar_vector_s v;

   bit <ADDR_WIDTH-1:0>  aligned_addr;


  int minval;
  int maxval;
  int wait_clks_before_next_ar;


  vif.set_arvalid(0b0);

  vif.wait_for_not_in_reset();

  forever {

    if (item == null) {
       readaddress_mbx.get(item);
      uvm_info("axi_driver::read_address",
                $sformatf("Item: %s", item.convert2string()),
                UVM_HIGH)

       axi_uvm_pkg::ar_from_class(.t(item), .v(v));
    }

    vif.wait_for_clks(.cnt(1));

      // if done with this xfer (write address is only one clock, done with valid & ready
       if (vif.get_arready_arvalid == 0b1) {
          readdata_mbx.put(item);
          item=null;

          minval=m_config.min_clks_between_ar_transfers;
          maxval=m_config.max_clks_between_ar_transfers;
          wait_clks_before_next_ar=$urandom_range(maxval,minval);

          // Check if delay wanted
          if (wait_clks_before_next_ar==0) {
             // if not, check if there's another item

            if (readaddress_mbx.try_get(item)) {

                axi_uvm_pkg::ar_from_class(.t(item), .v(v));
             }
          }
       }
       // Initialize values  <-no need

       // Update values <- No need in write address (only one clk per)

       // Write out
       if (item != null) {
          vif.write_ar(.s(v), .valid(0b1));
       }  else {// if (item != null)

    // No item for next clock, so close out bus
    // if (item == null) begin
         v.araddr  = 0x0;
         v.arid    = 0x0;
         v.arsize  = 0x0;
         v.arburst = 0x0;
         vif.write_ar(.s(v), .valid(0b0));
    // end

        if (wait_clks_before_next_ar > 0) {
           vif.wait_for_clks(.cnt(wait_clks_before_next_ar-1)); // -1 because another wait
                                                                // // at beginning of loop
        }
    }


    } // forever
}


task axi_driver::read_data() {

   axi_seq_item_r_vector_s  r_s;
   axi_seq_item_r_vector_s  r_q[$];
   axi_seq_item   item=null;
   axi_seq_item cloned_item=null;
   bit <ADDR_WIDTH-1:0>  read_addr;
   int beat_cntr=0;
   int beat_cntr_max=0;
   int Lower_Byte_Lane;
   int Upper_Byte_Lane;
   int offset;
   string msg_s;

  vif.enable_rready_toggle_pattern(.pattern(m_config.rready_toggle_pattern));

   forever {
      uvm_info(this.get_type_name(),
                "========> wait_for_read_data()",
                UVM_HIGH)

      vif.wait_for_read_data(.s(r_s));
      uvm_info(this.get_type_name(), "wait_for_read_data - DONE", UVM_HIGH)

      //  Can we just queue the data no matter what and
      // if the addresshasn'tarrived, we don't sit and poll continuosly
      // for and address.
      // What happens if we don't get an address until after wlast?
      r_q.push_back(r_s);

      if (item == null) {
        if (readdata_mbx.num() > 0) {
          readdata_mbx.get(item);
          $cast(cloned_item, item.clone());
          cloned_item.set_id_info(item);

          cloned_item.cmd=e_READ_DATA;
          cloned_item.data  = new[cloned_item.len];

          beat_cntr=0;
          beat_cntr_max=axi_pkg::calculate_axlen(.addr         (cloned_item.addr),
                                                 .burst_size   (cloned_item.burst_size),
                                                 .burst_length (cloned_item.len)) + 1;
        }  // if .num > 0
      } // if item == null

      // if anything in data queue, write it out
      if (item != null) {
         while (item != null && r_q.size() > 0) {

            r_s=r_q.pop_front();
            axi_pkg::get_beat_N_byte_lanes(.addr         (cloned_item.addr),
                                           .burst_size   (cloned_item.burst_size),
                                           .burst_length (cloned_item.len),
                                           .burst_type   (cloned_item.burst_type),
                                           .beat_cnt        (beat_cntr),
                                           .data_bus_bytes  (vif.get_data_bus_width()/8),
                                           .Lower_Byte_Lane  (Lower_Byte_Lane),
                                           .Upper_Byte_Lane (Upper_Byte_Lane),
                                           .offset          (offset));

            msg_s="";
           $sformat(msg_s, "%s beat_cntr:%0d",       msg_s, beat_cntr);
           $sformat(msg_s, "%s beat_cntr_max:%0d",   msg_s, beat_cntr_max);
           $sformat(msg_s, "%s data_bus_bytes:%0d",  msg_s, vif.get_data_bus_width()/8);
           $sformat(msg_s, "%s Lower_Byte_Lane:%0d", msg_s, Lower_Byte_Lane);
           $sformat(msg_s, "%s Upper_Byte_Lane:%0d", msg_s, Upper_Byte_Lane);
           $sformat(msg_s, "%s offset:%0d",          msg_s, offset);

           // `uvm_info("driver::read_data", msg_s, UVM_INFO)

           msg_s="data: 0x";
           for (int z=(vif.get_data_bus_width()/8)-1;z>=0;z--) {
             $sformat(msg_s, "%s%02x", msg_s, r_s.rdata[z*8+:8]);
           }
           // `uvm_info("driver::read_data", msg_s, UVM_INFO)

           for (int z=Lower_Byte_Lane;z <=Upper_Byte_Lane;z++) {
              if (offset < cloned_item.len) {
                 cloned_item.data[offset++] = r_s.rdata[z*8+:8];
              }
           }

           beat_cntr++;
           // if (r_s.rlast == 1'b1) begin // @Todo: count, dont rely on wlast?
           if (beat_cntr >= beat_cntr_max) {
              // ap.write(cloned_item);
              seq_item_port.put(cloned_item);
             item=null;
             beat_cntr=0;
           }  // if .wlast == 1
        } // while
     }// if
  }  // forever

}