44 uvm_analysis_port <axi_seq_item> ap;
55 new (
string name=
"axi_monitor", uvm_component parent=null);
71 super.new(name, parent);
78 super.build_phase(phase);
83 vif=axi_if_abstract::type_id::create(
"vif",
this);
88 super.connect_phase(phase);
123 original_item = axi_seq_item::type_id::create(
"original_item");
129 uvm_info(this.get_type_name(),
"wait_for_write_address - DONE", UVM_INFO)
131 $cast(item, original_item.clone());
140 $cast(cloned2_item, item.clone());
149 uvm_info(
"WRITE_ADDRESS", $sformatf(
"Item; %s", item.
convert2string()), UVM_HIGH)
186 uvm_info(this.get_type_name(),
187 "========> wait_for_write_data()",
191 uvm_info(this.get_type_name(),
"wait_for_write_data - DONE", UVM_HIGH)
202 $cast(cloned_item, item.clone());
204 cloned_item.
wstrb =
new[cloned_item.
len];
205 cloned_item.
data =
new[cloned_item.
len];
213 while (w_q.size() > 0) {
219 .burst_length (item.
len),
221 .beat_cnt (beat_cntr),
223 .Lower_Byte_Lane (Lower_Byte_Lane),
224 .Upper_Byte_Lane (Upper_Byte_Lane),
228 $sformat(msg_s,
"%s beat_cntr:%0d", msg_s, beat_cntr);
230 $sformat(msg_s,
"%s Lower_Byte_Lane:%0d", msg_s, Lower_Byte_Lane);
231 $sformat(msg_s,
"%s Upper_Byte_Lane:%0d", msg_s, Upper_Byte_Lane);
232 $sformat(msg_s,
"%s offset:%0d", msg_s, offset);
234 uvm_info(
"MONITOR::write_data", msg_s, UVM_HIGH)
238 $sformat(msg_s,
"%s%0b", msg_s, w_s.
wstrb[x]);
240 uvm_info(
"MONITOR::write_data", msg_s, UVM_HIGH)
242 for (
int x=Lower_Byte_Lane;x <=Upper_Byte_Lane;x++) {
250 .burst_length(item.
len),
252 .beat_cnt(beat_cntr),
256 if (w_s.
wstrb[x] == 0b1) {
257 uvm_info(
"M_MEMORY.WRITE",
258 $sformatf(
"[0x%0x] = 0x%2x", write_addr, w_s.
wdata[x*8+:8]),
266 if (w_s.
wlast == 0b1) {
268 ap.write(cloned_item);
289 item = axi_seq_item::type_id::create(
"item");
292 uvm_info(this.get_type_name(),
"wait_for_write_response - DONE", UVM_HIGH)
294 $cast(cloned_item, item.clone());
297 ap.write(cloned_item);
333 int valid_assert_bit;
340 item = axi_seq_item::type_id::create(
"item");
348 uvm_info(this.get_type_name(),
"wait_for_read_address - DONE", UVM_HIGH)
351 $cast(cloned_item, item.clone());
355 cloned_item.
data=
new[cloned_item.
len];
359 uvm_info(
"axi_monitor::read_address",
367 cloned_item.
valid=
new[cloned_item.
len];
368 j=cloned_item.
valid.size();
369 for (
int i=0;i <j;i++) {
370 cloned_item.
valid[i] = $random;
374 j=cloned_item.
valid.size();
375 for (
int i=0;i <j;i++) {
376 if (cloned_item.
valid[i] == 0b1) {
382 if (valid_asserts==0) {
383 valid_assert_bit=$urandom_range(j-1,0);
384 cloned_item.
valid[valid_assert_bit] = 0b1;
385 uvm_info(
"axi_monitor",
386 $sformatf(
"All zeros. Settin bit %0d to 1", valid_assert_bit),
391 for (
int i=0;i <j;i++) {
392 $sformat(valid_s,
"%s%0b", valid_s, cloned_item.
valid[i]);
398 .burst_length (cloned_item.
len)) + 1;
400 for (
int beat_cntr=0;beat_cntr <beat_cnt_max;beat_cntr++) {
404 .burst_length (cloned_item.
len),
406 .beat_cnt(beat_cntr),
408 .Lower_Byte_Lane(Lower_Byte_Lane),
409 .Upper_Byte_Lane(Upper_Byte_Lane),
413 $sformat(msg_s,
"%s beat_cntr:%0d", msg_s, beat_cntr);
414 $sformat(msg_s,
"%s beat_cnt_max:%0d", msg_s, beat_cnt_max);
416 $sformat(msg_s,
"%s Lower_Byte_Lane:%0d", msg_s, Lower_Byte_Lane);
417 $sformat(msg_s,
"%s Upper_Byte_Lane:%0d", msg_s, Upper_Byte_Lane);
418 $sformat(msg_s,
"%s offset:%0d", msg_s, offset);
421 uvm_info(
"axi_monitor::read_address", msg_s, UVM_HIGH)
424 for (
int x=Lower_Byte_Lane;x <=Upper_Byte_Lane;x++) {
429 .addr(cloned_item.
addr),
431 .burst_length(cloned_item.
len),
433 .beat_cnt(beat_cntr),
437 uvm_info(
"M_MEMORY.READ",
438 $sformatf(
"[0x%0x] = 0x%2x", read_addr,
m_memory.
read(read_addr)),
448 uvm_info(
"AR_TO_CLASS-poost", $sformatf(
"%s", cloned_item.
convert2string()), UVM_HIGH)
456 $cast(cloned2_item, cloned_item.clone());
464 ap.write(cloned_item);
496 uvm_info(this.get_type_name(),
497 "========> wait_for_read_data()",
501 uvm_info(this.get_type_name(),
"wait_for_read_data - DONE", UVM_HIGH)
511 $cast(cloned_item, item.clone());
514 cloned_item.
data =
new[cloned_item.
len];
520 while (r_q.size() > 0) {
524 if (r_s.
rlast == 0b1) {
525 ap.write(cloned_item);
bit< C_AXI_LEN_WIDTH-1:0 > calculate_axlen(input bit< C_AXI_ADDR_WIDTH-1:0 > addr, input bit< 2:0 > burst_size, input shortint burst_length)
calculate awlen or arlen
mailbox< axi_seq_item > readdata_mbx
string convert2string()
Convert item's variable into one printable string.
Extremely simple memory model with just write() and read() methods.
logic< C_AXI_DATA_WIDTH/8-1:0 > wstrb
This packed struct is used to send read data channel information between the DUT and TB...
This packed struct is used to send write address channel information between the DUT and TB...
uvm_analysis_port< axi_seq_item > driver_activity_ap
virtual task wait_for_write_data(output axi_seq_item_w_vector_s s)
Wait for a valid write data to be acknowledged and return it.
logic< C_AXI_DATA_WIDTH-1:0 > wdata
task read_address()
monitors Read Address channel
automatic void aw_to_class(ref axi_seq_item t, input axi_seq_item_aw_vector_s v)
Pull values out of a axi_seq_item_aw_vector_s and stuffs them into an axi_seq_item.
bit< C_AXI_ADDR_WIDTH-1:0 > get_next_address(input bit< C_AXI_ADDR_WIDTH-1:0 > addr, input bit< 2:0 > burst_size, input shortint burst_length, input bit< 1:0 > burst_type, input int beat_cnt, input int lane, input int data_bus_bytes)
Get next address for reading/writing to memory.
task write_data()
monitors Write Data channel
virtual int get_data_bus_width()
returns data bus width
monitors all 5 channels for activity
rand bit< ADDR_WIDTH-1:0 > addr
virtual void write(input bit< ADDR_WIDTH-1:0 > addr, input bit< 7:0 > data)
Writes into memory.
abstract base class for polymorphic interface class (axi_if_concrete) for AXI UVM environment ...
virtual bit< 7:0 > read(input bit< ADDR_WIDTH-1:0 > addr)
Reads from memory.
rand logic< 2:0 > burst_size
automatic void b_to_class(ref axi_seq_item t, input axi_seq_item_b_vector_s v)
return values from a axi_seq_item_b_vector_s and return an axi_seq_item
virtual task wait_for_write_response(output axi_seq_item_b_vector_s s)
Wait for a valid write response to be acknowledged and return it.
void connect_phase(uvm_phase phase)
void build_phase(uvm_phase phase)
Creates the analysis port and virtual interface.
task read_data()
monitors Read Data channel and sends out TLM pkt Loop Wait for activity on the Read Data Channel...
automatic void ar_to_class(ref axi_seq_item t, input axi_seq_item_ar_vector_s v)
Pull values out of a axi_seq_item_ar_vector_s and stuffs them into an axi_seq_item.
virtual task wait_for_write_address(output axi_seq_item_aw_vector_s s)
Wait for a valid write address to be acknowledged and return it.
task write_address()
monitors Write Address channel
This packed struct is used to send write data channel information between the DUT and TB...
virtual task wait_for_read_data(output axi_seq_item_r_vector_s s)
Wait for a valid read data to be acknowledged and return it.
uvm_component_utils(axi_monitor) uvm_analysis_port< axi_seq_item > ap
mailbox< axi_seq_item > writedata_mbx
void get_beat_N_byte_lanes(input bit< C_AXI_ADDR_WIDTH-1:0 > addr, input bit< 2:0 > burst_size, input shortint burst_length, input bit< 1:0 > burst_type, input int beat_cnt, input int data_bus_bytes, output int Lower_Byte_Lane, output int Upper_Byte_Lane, output int offset)
return byte lanes that contain valid data
task write_response()
monitors Write Response channel and sends out TLM pkt Loop Wait for activity on the Write Response Ch...
virtual task wait_for_read_address(output axi_seq_item_ar_vector_s s)
Wait for a valid read address to be acknowledged and return it.
new(string name="axi_monitor", uvm_component parent=null)
Constructor.
axi_agent_config m_config
This packed struct is used to send write response channel information between the DUT and TB...
Configuration object for an axi_agent.
rand logic< 1:0 > burst_type
contains all data and functions related to axi and usage
This packed struct is used to send read address channel information between the DUT and TB...
task run_phase(uvm_phase phase)
Starts the monitoring threads.